System and method for controlling variations of switching frequency

ABSTRACT

System and method for providing frequency control to a power converter. The system includes a pseudorandom signal generator configured to generate a digital signal. The digital signal is associated with at least an N-bit datum, and N is a positive integer. Additionally, the system includes a digital-to-analog converter configured to receive the digital signal and generate a first control signal, an output signal generator configured to receive the first control signal and generate at least a first output signal associated with a frequency, and a pulse-width-modulation generator configured to receive at least the first output signal. The N-bit datum represents a pseudorandom number.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No.______ (East IP Ref. No. 05NI2173-1365-SMY), filed Mar. 30, 2005,entitled “System and Method for Controlling Variations of SwitchingFrequency in Power Converters,” by Inventors Jun Ye, Zhen Zhu, ShifengZhao, Lieyi Fang, and Zhiliang Chen, commonly assigned, incorporated byreference herein for all purposes.

The following two commonly-owned co-pending applications, including thisone, are being filed concurrently and the other one is herebyincorporated by reference in its entirety for all purposes:

1. U.S. patent application Ser. No. ______, in the name of Jun Ye, ZhenZhu, Shifeng Zhao, Lieyi Fang, and Zhiliang Chen, titled, “System andMethod for Adaptive Switching Frequency Control,” (Attorney DocketNumber 025748-000200US); and

2. U.S. patent application Ser. No. ______, in the name of Jun Ye, ZhenZhu, Shifeng Zhao, Lieyi Fang, and Zhiliang Chen, titled, “System andMethod for Controlling Variations of Switching Frequency,” (AttorneyDocket Number 025748-000300US).

STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSOREDRESEARCH OR DEVELOPMENT

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REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAMLISTING APPENDIX SUBMITTED ON A COMPACT DISK

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BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuits. Moreparticularly, the invention provides a system and method for controllingfrequency variations. Merely by way of example, the invention has beenapplied to a power converter. But it would be recognized that theinvention has a much broader range of applicability.

Power converters are widely used for consumer electronics such asportable devices. The power converters can convert electric power fromone form to another form. As an example, the electric power istransformed from alternate current (AC) to direct current (DC), from DCto AC, from AC to AC, or from DC to DC. Additionally, the powerconverters can convert the electric power from one voltage level toanother voltage level. The power converters include linear convertersand switch-mode converters.

The switch-mode converters often need to meet certain requirements onelectromagnetic interference (EMI). A single switching frequency and itsharmonics can cause EMI problems. To suppress EMI, the switchingfrequency is often varied by clock jittering for conventionalswitch-mode power converters.

For example, the clock jittering is generated by an analog circuit forfrequency variations. The analog circuit provides a frequency variationsignal at a frequency much lower than the switching frequency of thepower converter. For example, the switching frequency is in the tens ofkilo-Hz range, and the frequency of the frequency variation signal iseven lower. Accordingly, the analog circuit often needs a largecapacitor area and is expensive to implement.

In another example, the clock jittering is generated by a digitalcircuit. The digital circuit can use a counter to generate a frequencyvariation signal. But the frequency variation signal often has a fixedpattern without scrambling. The energy spreading may not be uniform inthe frequency band of interest. In yet another example, the frequencyvariation is controlled by an external signal such as a power supplyvoltage of an integrated circuit (IC) system. But the range of frequencyvariation is often limited. Additionally, change of the switchingfrequency with the power supply voltage often makes the switch-modepower converter difficult to design.

Hence it is highly desirable to improve techniques for controllingfrequency variations.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to integrated circuits. Moreparticularly, the invention provides a system and method for controllingfrequency variations. Merely by way of example, the invention has beenapplied to a power converter. But it would be recognized that theinvention has a much broader range of applicability,

According to one embodiment of the present invention, a system forproviding frequency control to a power converter is provided. The systemincludes a pseudorandom signal generator configured to generate adigital signal. The digital signal is associated with at least an N-bitdatum, and N is a positive integer. Additionally, the system includes adigital-to-analog converter configured to receive the digital signal andgenerate a first control signal, an output signal generator configuredto receive the first control signal and generate at least a first outputsignal associated with a frequency, and a pulse-width-modulationgenerator configured to receive at least the first output signal. TheN-bit datum represents a pseudorandom number.

According to another embodiment of the present invention, a system forproviding a pseudorandom signal includes a shift register configured toreceive a first input signal and a second input signal and generate adigital signal. The shift register includes m flip-flops, and m is apositive integer. Additionally, the system includes a processing deviceconfigured to receive a plurality of signals and generate the firstinput signal. The plurality of signals represent data stored in aplurality of flip-flops respectively, and the plurality of flip-flopsare selected from the m flip-flops. Moreover, the system includes adigital-to-analog converter configured to receive the digital signal andgenerate an analog signal associated with a signal strength. The digitalsignal represents at least an N-bit datum, and N is a positive integer.The N-bit datum corresponds to N flip-flops, and the N flip-flops isselected from the m flip-flops.

According to yet another embodiment of the present invention, a methodfor providing frequency control to a power converter includes generatinga digital signal. The digital signal is associated with at least anN-bit datum, and N is a positive integer. Additionally, the methodincludes receiving the digital signal, processing information associatedwith the digital signal, and generating a first control signal based onat least information associated with the digital signal. The firstcontrol signal is an analog signal. Moreover, the method includesreceiving the first control signal, processing information associatedwith the first control signal, and generating at least a first outputsignal related to a frequency based on at least information associatedwith the first control signal. The N-bit datum represents a pseudorandomnumber.

According to yet another embodiment of the present invention, a methodfor providing a pseudorandom signal includes receiving a plurality ofsignals from a shift register, processing information associated withthe plurality of signals, and generating a first input signal based onat least information associated with the plurality of signals.Additionally, the method includes receiving the first input signal and asecond input signal by the shift register, processing informationassociated with the first input signal and the second input signal, andgenerating a digital signal based on at least information associatedwith the first input signal and the second input signal by an M-sequenceprocess. Moreover, the method includes processing information associatedwith the digital signal, and generating an analog signal related to asignal strength based on at least information associated with thedigital signal. The digital signal represents at least an N-bit datum,and N is a positive integer. The N-bit datum represents a pseudorandomnumber.

Many benefits are achieved by way of the present invention overconventional techniques. For example, some embodiments of the presentinvention can reduce electromagnetic interference of a switch-mode powerconverter. For example, the switch-mode converter is an off-line powerconverter. Certain embodiments of the present invention provideswitching frequency variations to a switch-mode power converter. Someembodiments of the present invention avoid a strong single tone at afixed frequency and the harmonics in a switch-mode power converter.Certain embodiments of the present invention can spread theelectromagnetic interference power within a frequency range for aswitch-mode power converter. For example, the randomization of theswitching frequency can make the EMI power spectrum substantiallyuniform in a frequency band around a mean switching frequency and thehigh order harmonics. Some embodiments of the present invention providefrequency variations according to a frequency modulation index M_(f).For example, the frequency modulation index M_(f) is determined by theEMI requirement of the switch-mode power converter.

Certain embodiments of the present invention use a digital circuit forfrequency variation. The digital circuit is portable, and can be easilymigrated for different integrated circuit manufacturing processes. Someembodiments of the present invention provide frequency variations to aclock signal by a pseudorandom signal. For example, the pseudorandomsignal is a M-sequence signal. Certain embodiments of the presentinvention use a frequency variation controller including an m-stageM-sequence generator and an N-bit digital-to-analog converter. Forexample, the m-stage M-sequence generator includes an m-stage linearshift register. In another example, the digital-to-analog converteroperates either in the voltage mode or the current mode. In yet anotherexample, the output of the digital-to analog converter is used tocontrol frequency variations of an oscillator in a switch-mode powerconverter. In yet another example, the clock signal generated by theoscillator is fed into the linear shift register.

Some embodiments of the present invention use an oscillator controlledby voltage or current signals. For example, the control signals aregenerated by a frequency variation generator and/or a dead-timecontroller. In another example, the oscillator generates a clock signaland a ramping signal. The clock signal and the ramping signal do nothave a constant frequency. The frequency is randomized and shuffled overtime. In yet another example, the charge and discharge current in theoscillator is modulated by a pseudorandom signal. The modulated chargeand discharge current determine the oscillation frequency and hence theswitching frequency in the switch-mode power converter.

Various additional objects, features and advantages of the presentinvention can be more fully appreciated with reference to the detaileddescription and the accompanying drawings that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified system for controlling frequency variationaccording to an embodiment of the present invention;

FIG. 2 is a simplified diagram showing frequency variations according toan embodiment of the present invention;

FIG. 3 is a simplified diagram for frequency variation generatoraccording to an embodiment of the present invention;

FIG. 4 is a simplified system for controlling frequency variationaccording to another embodiment of the present invention;

FIG. 5 is a simplified system for frequency control according to anotherembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to integrated circuits. Moreparticularly, the invention provides a system and method for controllingfrequency variations. Merely by way of example, the invention has beenapplied to a power converter. But it would be recognized that theinvention has a much broader range of applicability.

FIG. 1 is a simplified system for controlling frequency variationaccording to an embodiment of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. A system 100 includes apseudorandom signal generator 110, an N-bit digital-to-analog converter120, a signal generator 140, and a pulse-width-modulation (PWM)generator 160. Although the above has been shown using a selected groupof components for the system 100, there can be many alternatives,modifications, and variations. For example, some of the components maybe expanded and/or combined. Other components may be inserted to thosenoted above. Depending upon the embodiment, the arrangement ofcomponents may be interchanged with others replaced. For example, thePWM generator 160 is replaced by another component receiving at least anoutput signal of the signal generator 140. Further details of thesecomponents are found throughout the present specification and moreparticularly below.

The pseudorandom signal generator 110 outputs a digital signal 130 tothe N-bit digital-to-analog (D/A) converter 120. For example, thepseudorandom signal generator 110 includes an m-stage M-sequencegenerator. m is a positive integer. In another example, N is a positiveinteger. The D/A converter 120 generates a control signal 132 based onthe digital signal 130. In one embodiment, the control signal 132 is inthe current domain. In another embodiment, the control signal is in thevoltage domain. For example, the control signal 132 is modulated by thedigital signal 130. In another example, the control signal 132 is apseudorandom signal. In yet another example, the pseudorandom signalgenerator 110 and the N-bit D/A converter 120 form a clock randomizer.

The control signal 132 is received by the signal generator 140. Forexample, the signal generator 140 is an output signal generator. Thesignal generator 140 outputs a clock signal 150 and a ramping signal 152based on the control signal 132. In one embodiment, the signal generator140 includes an oscillator. For example, the oscillator is a voltagecontrolled oscillator (VCO). In another example, the oscillator is acurrent controlled oscillator (ICO). The oscillation frequency ismodulated with respect to time by the control signal 132. For example,the oscillation frequency is randomized around a mean frequency for apredetermined time period.

The clock signal 150 and the ramping signal 152 are received by the PWMgenerator 160. Additionally, the clock signal 150 is also received bythe pseudorandom signal generator 110. In one embodiment, the PWMgenerator 160 also receives a voltage feedback signal 162 and a currentsensing signal 164, and generates a PWM signal 166. For example, the PWMsignal 166 is used to turn on or off a power switch in a switch-modepower converter. In another example, the ramping signal 152 is used forslop compensation in the switch-mode power converter. In yet anotherexample, the clock signal 150 is used to determine the switchingfrequency of the switch-mode power converter. In one embodiment, theswitch-mode power converter is an off-line power converter. In anotherembodiment, the power converter operates in a current mode. In yetanother example, the PWM generator 160 is configured to control aswitching frequency and a pulse width for a power converter.

FIG. 2 is a simplified diagram showing frequency variations according toan embodiment of the present invention. This diagram is merely anexample, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications. As shown in FIG. 2, the frequency f changes over timet. For example, the frequency f varies between a maximum frequencyf_(max) and a minimum frequency f_(min) around a mean frequencyf_(mean). For example, the frequency modulation index M_(F) is definedas follows: $\begin{matrix}{M_{f} = \frac{f_{\max} - f_{\min}}{f_{\max} + f_{\min}}} & \left( {{Equation}\quad 1} \right)\end{matrix}$

For example, the difference between f_(max) and f_(min) is determined bythe magnitude of the control signal 132 generated by the pseudorandomsignal generator 110 and the N-bit D/A converter 120. In one embodiment,the frequency f represents the frequency of the clock signal 150generated by the signal generator 140. In another embodiment, thefrequency f represents a switching frequency of the switch-mode powerconverter controlled by the PWM generator 160. Accordingly, theelectromagnetic interference (EMI) power is spread in a frequency rangeinstead of a single frequency f_(mean) according to an embodiment of thepresent invention.

FIG. 3 is a simplified diagram for frequency variation generatoraccording to an embodiment of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. A system 300 includes anm-stage M-sequence generator 310 and an N-bit digital-to-analog (D/A)converter 320. Although the above has been shown using a selected groupof components for the system 300, there can be many alternatives,modifications, and variations. For example, some of the components maybe expanded and/or combined. Other components may be inserted to thosenoted above. Depending upon the embodiment, the arrangement ofcomponents may be interchanged with others replaced. For example, them-stage M-sequence generator 310 is replaced by another type ofpseudorandom signal generator. Further details of these components arefound throughout the present specification and more particularly below.

The m-stage M-sequence generator 310 includes a linear feedback shiftregister 330 and a logic component 340. For example, the m-stageM-sequence generator can provide the maximum length pseudo-random numberfor a given m-stage and maximize the randomization. The linear shiftregister 330 includes flip-flops 1, 2, . . . , m−1, and m, and receivesa clock signal 332. m is a positive integer. In response to the clocksignal 332, the datum stored in a flip-flop is replaced by the datumtransferred from the flip-flop at an earlier stage. For example, thedatum stored in flip-flop 1 is transferred to flip-flop 2, the datumstored in flip-flop 2 is transferred to flip-flop 3, . . . , and thedatum stored in flip-flop m−1 is transferred to flip-flop m.Additionally, the datum stored in flip-flop 1 is replaced by an datumrepresented by an output signal 334 generated by the logic component340.

The logic component 340 receives input signals 342 from selectedflip-flops of the linear shift register 330. For example, the logiccomponent 340 includes a processing device. Each input signal representsa datum stored in the corresponding flip-flop. The input signals areprocessed according to a predetermined logic, and the logic componentgenerates the output signal 334. In one embodiment, the logic component340 includes an exclusive OR (XOR) gate.

The N-bit digital-to-analog (D/A) converter 320 receives a digitalsignal. N is a positive integer. The digital signal includes signals336, each of which represents the datum stored in one of N flip-flops.The N flip-flops are selected from the flip-flops of the linear shiftregister 330. The digital signal received by the D/A converter 320represents an N-bit binary datum. Each bit represents the datum storedin one of the N flip-flops. Additionally, the D/A converter 320 receivesa reference signal 322. The reference signal 322 is used to determine amaximum signal level S_(max) and a minimum signal level S_(min). Inresponse to the received digital signal, the D/A converter 320 generatesan output signal 324. The output signal 324 ranges from S_(min) toS_(max). For example, the output signal 324 is in the voltage domain. Inanother example, the output signal 324 is in the current domain.

The system 300 has various applications. In one embodiment, the system300 is used for the system 100. For example, the m-stage M-sequencegenerator 310 is the m-stage M-sequence generator 110. The D/A converter320 is the D/A converter 120. The clock signal 332 is the clock signal150, and the output signal 324 is the control signal 132. For example,the maximum signal level S_(max) and the minimum signal level S_(min)correspond to the maximum frequency f_(max) and the minimum frequencyf_(min) respectively.

FIG. 4 is a simplified system for controlling frequency variationaccording to another embodiment of the present invention. This diagramis merely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. A system 400 includes apseudorandom signal generator 410, an N-bit digital-to-analog converter420, a signal generator 440, a pulse-width-modulation (PWM) generator460, a sensing system 1410, a compensation controller 1420, and adead-time controller 1230. Although the above has been shown using aselected group of components for the system 400, there can be manyalternatives, modifications, and variations. For example, some of thecomponents may be expanded and/or combined. Other components may beinserted to those noted above. Depending upon the embodiment, thearrangement of components may be interchanged with others replaced. Forexample, the PWM generator 460 is replaced by another componentreceiving at least an output signal of the signal generator 440. Furtherdetails of these components are found throughout the presentspecification and more particularly below.

The pseudorandom signal generator 410 outputs a digital signal 430 tothe N-bit digital-to-analog (D/A) converter 420. For example, thepseudorandom signal generator includes an m-stage M-sequence generator.m is a positive integer. In another example, N is a positive integer.The D/A converter 420 generates a control signal 432 based on thedigital signal 430. In one embodiment, the control signal 432 is in thecurrent domain. In another embodiment, the control signal is in thevoltage domain. For example, the control signal 432 is modulated by thedigital signal 430. In another example, the control signal 432 is apseudorandom signal. In yet another example, the pseudorandom signalgenerator 410 and the N-bit D/A converter 420 form a clock randomizer.

The control signal 432 is received by the signal generator 440.Additionally, the signal generator 440 receives control signals 1222 and1232 from the compensation controller 1420 and the dead-time controller1230 respectively. For example, the signal generator 440 is an outputsignal generator. The signal generator 440 outputs a clock signal 450and a ramping signal 452 based on the control signals 432, 1222 and1232. In one embodiment, the signal generator 440 includes anoscillator. For example, the oscillator is a voltage controlledoscillator (VCO). In another example, the oscillator is a currentcontrolled oscillator (ICO). The oscillation frequency is modulated withrespect to time by the control signal 432. For example, the oscillationfrequency is randomized around a mean frequency for a predetermined timeperiod.

The clock signal 450 and the ramping signal 452 are received by the PWMgenerator 460. Additionally, the clock signal 450 is also received bythe pseudorandom signal generator 410. In one embodiment, the PWMgenerator 460 also receives a voltage feedback signal 462 and a currentsensing signal 464, and generates a PWM signal 466. For example, the PWMsignal 466 is used to turn on or off a power switch in a switch-modepower converter. In another example, the ramping signal 452 is used forslop compensation in the switch-mode power converter. In yet anotherexample, the clock signal 450 is used to determine the switchingfrequency of the switch-mode power converter. In one embodiment, theswitch-mode power converter is an off-line power converter. In anotherembodiment, the power converter operates in a current mode.

The dead-time controller 1230 receives a load signal 1234 and generatesthe control signal 1232. The load signal 1234 represents the level ofoutput load for the switch-mode converter. For example, the load signal1234 includes a control voltage which increases with the output load. Asanother example, the load signal 1234 is generated by a feedback loop.In response to the load signal 1234, the dead-time controller 1230outputs the control signal 1232 to the signal generator 440. The signalgenerator 440 uses the control signal 1232 to perform frequency control.

The sensing system 1410 receives an input voltage 1224 and generates acontrol signal 1430. The control signal 1430 represents the magnitude ofthe input voltage 1224. In one embodiment, the control signal 1430 is inthe current domain. In another embodiment, the control signal 1430 is inthe voltage domain. The control signal 1430 is received by thecompensation controller 1420, which generates the control signal 1222 inresponse.

The control signal 1222 is received by the signal generator 440. Forexample, the signal generator 440 includes an oscillator. In anotherexample, the signal generator 440 outputs the ramping signal 452 whoseslope of signal strength as a function of time is adjusted based on thecontrol signal 1222. Additionally, the signal generator 440 outputs theclock signal 450. For example, the clock signal 450 has the samefrequency as the ramping signal 452. In another example, the clocksignal 450 is used by the PWM generator 460 to control switchingfrequency of the switch-mode power converter.

As discussed above, the frequency of the clock signal 450 is controlledby the control signal 432 generated by the N-bit digital-to-analogconverter 420 and the control signal 1232 generated by the dead-timecontroller 1230 respectively. For example, the control signal 432determines the mean frequency of the clock signal 450, and the controlsignal 1232 determines the frequency variations of the clock signal 450as shown in FIG. 2.

FIG. 5 is a simplified system for frequency control according to anotherembodiment of the present invention. This diagram is merely an example,which should not unduly limit the scope of the claims. One of ordinaryskill in the art would recognize many variations, alternatives, andmodifications. A system 1700 includes a frequency variation generator1710, a compensator 1720, switches 1730, 1732 and 1734, NANDs 1740 and1742, AND 1744, comparators 1750, 1752 and 1754, inverters 1760 and1762, capacitors 1770 and 1772, current sources 1780, 1782, 1784, 1786and 1788. Although the above has been shown using a selected group ofcomponents for the system 1700, there can be many alternatives,modifications, and variations. For example, some of the components maybe expanded and/or combined. Other components may be inserted to thosenoted above. Depending upon the embodiment, the arrangement ofcomponents may be interchanged with others replaced. Further details ofthese components are found throughout the present specification and moreparticularly below.

The capacitor 1770 is charged or discharged through the switch 1730 (SH)or the switch 1732 (SL) respectively. Between the discharging phase(T_(off)) and the charging phase (T_(on)), a dead time T_(dead) can beinserted between T_(on) and T_(off) by keeping both switches 1730 and1732 open. The outputs of comparators 1750 (A1) and 1752 (A2) arelatched by an RS flip-flop. The RS flip-flop includes the NANDs 1740(NAND1) and 1742 (NAND2). The comparators 1750 (A1) and 1752 (A2) arevoltage clamping comparators with threshold voltages 1840 (V_(H)) and1842 (V_(L)) respectively. The voltage 1830 at one terminal of thecapacitor 1770 has a voltage range that is equal to the differencebetween the threshold voltages 1842 and 1840.

The capacitor 1772 (C_(g)), the current source 1784 (I_(g)), the switch1734 (SG), and the comparator 1754 (A3) are used for dead-timemodulation. If a control voltage 1810 (V_(ctrl)) is smaller than athreshold voltage (V_(th) _(—) _(g)), a voltage 1814 at one terminal ofthe capacitor 1772 begins to rise from the control voltage 1810 to thethreshold voltage 1812 after a discharging phase (T_(off)) ends for thecapacitor 1770 (C₀). For example, the rise of the voltage 1814 issupported by the current source 1784. At the end of the dischargingperiod, the switch 1734 becomes open.

When the voltage 1814 reaches the threshold voltage 1812, a signal 1820generated by the AND 1744 (AND1) is used to close the switch 1730 (SH).Subsequently, the voltage 1830 for the capacitor 1770 starts to rise,and the charging phase (T_(on)) begins. In one embodiment, the dead timeT_(dead) is the period when the switches 1730 and 1732 are both open.During the dead time, the voltage 1830 is kept constant over time.

As shown in FIG. 5, the dead time T_(dead) is proportional to thedifference between the threshold voltage (V_(th) _(—) _(g)) and thecontrol voltage 810 (V_(ctrl)) if V_(ctrl) is less than V_(th) _(—)_(g). For example, T_(dead) increases with decreasing V_(ctrl) ifV_(ctrl) is less than V_(th) _(—) _(g). The oscillation frequency of thevoltage 1830 decreases with decreasing V_(ctrl). For example, thecontrol voltage 1810 (V_(ctrl)) represents the level of output load forthe switch-mode converter. In another example, V_(ctrl) increases withthe output load. In yet another example, V_(ctrl) is generated by afeedback loop. If V_(ctrl) is greater than or equal to V_(th) _(—) _(g),the dead time T_(dead) equals to zero.

In another embodiment, V_(th) _(—) _(g) corresponds a threshold outputload, and V_(ctrl), varies with the output load. For example, V_(ctrl),increases with the output load. As shown in FIG. 5, T_(dead) increaseswith the decreasing output load if the output load is less than thethreshold output load. For example, T_(dead) increases with thedecreasing output load if the output load is less than the thresholdoutput load but more than another threshold output load. If the outputload is more than or equal to the threshold output load, the dead timeT_(dead) equals to zero.

In yet another embodiment, the charging time T_(on) and the dischargingtime T_(off) each are constant with respect to V_(ctrl). For example,V_(ctrl) varies with the output load. The charging time T_(on) and thedischarging time T_(off) each are constant with respect to output load.

In yet another embodiment, time periods for charging phase, dischargingphase, and dead time phase are determined as follows: $\begin{matrix}{T_{on} = \frac{\left( {V_{H} - V_{L}} \right) \times C_{O}}{I_{C} + I_{CM}}} & \left( {{Equation}\quad 2} \right) \\{T_{off} = \frac{\left( {V_{H} - V_{L}} \right) \times C_{O}}{I_{D} + I_{DM}}} & \left( {{Equation}\quad 3} \right) \\{{T_{dead} = {{\frac{\left( {V_{th\_ g} - V_{ctrl}} \right) \times C_{g}}{I_{g}}\quad{if}\quad V_{th\_ g}} > V_{ctrl}}}\quad} & \left( {{Equation}\quad 4} \right) \\{T_{dead} = {{0\quad{if}\quad V_{th\_ g}} \leq V_{ctrl}}} & \left( {{Equation}\quad 5} \right)\end{matrix}$

where T_(on), T_(off), and T_(dead) are time periods for charging phase,discharging phase, and dead-time phase respectively. T_(on) depends onthe sum of current sources 1780 (I_(C)) and 1786 (I_(CM)) and thedifference between the threshold voltages 1840 (V_(H)) and 1842 (V_(L)).T_(off) depends on the sum of current sources 1782 (I_(D)) and 1788(I_(DM)). For example, the current sources 1786 (I_(CM)) and 1788(I_(DM)) are voltage controlled current source. Additionally, thefrequency F_(S) of the voltage 1830 is defined as follows:$\begin{matrix}{F_{S} = \frac{1}{T_{on} + T_{off} + T_{dead}}} & \left( {{Equation}\quad 6} \right)\end{matrix}$

As shown in FIG. 5, the current sources 1786 (I_(CM)) and 1788 (I_(DM))are modulated by control signals 1860 and 1862 from the frequencyvariation generator 1710. The frequency F_(S) is modulated by thefrequency variation generator 1710 if V_(th) _(—) ^(g)≦V_(ctrl). IfV_(th) _(—) _(g)>V_(ctrl), the frequency F_(S) is modulated by thefrequency variation generator 1710 and the components used for dead timecontrol.

In one embodiment, the control signals 1860 and 1862 each represent apseudorandom signal. Accordingly, the current sources 1786 (I_(CM)) and1788 (I_(DM)) are controlled by the pseudorandom signals. Based onEquations 2-6, the switching frequency of the switch-mode powerconverter is modulated by the pseudorandom signals.

In one embodiment, the frequency variation generator 1710 includes thepseudorandom signal generator 110 and the N-bit digital-to-analogconverter 120 as shown in FIG. 1. In another embodiment, the frequencyvariation generator 1710 includes the m-stage M-sequence generator 310and the N-bit digital-to-analog converter 320 as shown in FIG. 3. In yetanother embodiment, the frequency variation generator 1710 includes thepseudorandom signal generator 410 and the N-bit digital-to-analogconverter 420 as shown in FIG. 4.

The current sources 1780 (I_(C)) and 1782 (I_(D)), and the thresholdvoltages 1840 (V_(H)) and 1842 (V_(L)) are modulated by the compensator1720. The compensator 1720 receives an input voltage 1850. As shown inFIG. 5, the voltage 1830 increases with time at a slope during thecharging phase (T_(on)), and decreases with time at another slope duringthe discharging phase (T_(off)). Both slopes vary with the input voltage1850. For example, the slopes vary with the input voltage 1850 within apredetermined voltage range. In another example, the slopes are constantwith respect to the control voltage 1810 (V_(ctrl)), but vary withrespect to the input voltage 1850.

As discussed above and further emphasized here, FIG. 5 is merely anexample, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications. In one embodiment, the voltage 1830 is used as aramping signal, and the signal 1820 is used as a clock signal. Forexample, the ramping signal and the clock signal are received by a PWMgenerator. The PWM generator uses the ramping signal to provide slopecompensation. For example, the slope compensation ratio is constantregardless of the input voltage 1850. Additionally, the PWM generatoruses the clock signal to control switching frequency.

As discussed above, the frequency F_(S) is modulated by varying thecurrent sources 1786 (I_(CM)) and 1788 (I_(DM)) with the control signals1860 and 1862. The current sources 1786 (I_(CM)) and 1788 (I_(DM)) alsoaffect the slop of the voltage 1830. For example, the voltage 1830 isused as a ramping signal to provide slope compensation. If the frequencymodulation is small, effect of the slop change on loop stability isnegligible.

In another embodiment, the system 1700 is used as the system 400. Forexample, the voltage 1830 is the ramping signal 452, and the signal 1820is the clock signal 450. In another example, the compensator 1720includes the sensing system 1410 and the compensation controller 1420.In yet another example, the control voltage 1810 is the load signal1234. In yet another example, the input voltage 1850 is the inputvoltage 1224. In yet another embodiment, at least part of the system1700 is used as the system 100. For example, the voltage 1830 is theramping signal 152, and the signal 1820 is the clock signal 150. In yetanother embodiment, the system 100, 300, or 1700 is a part of the powerconverter.

According to yet another embodiment of the present invention, a methodfor providing frequency control to a power converter includes generatinga digital signal. The digital signal is associated with at least anN-bit datum, and N is a positive integer. Additionally, the methodincludes receiving the digital signal, processing information associatedwith the digital signal, and generating a first control signal based onat least information associated with the digital signal. The firstcontrol signal is an analog signal. Moreover, the method includesreceiving the first control signal, processing information associatedwith the first control signal, and generating at least a first outputsignal related to a frequency based on at least information associatedwith the first control signal. The N-bit datum represents a pseudorandomnumber. For example, the method can be performed by the system 100, 300,400, and/or 1700.

According to yet another embodiment of the present invention, a methodfor providing a pseudorandom signal includes receiving a plurality ofsignals from a shift register, processing information associated withthe plurality of signals, and generating a first input signal based onat least information associated with the plurality of signals.Additionally, the method includes receiving the first input signal and asecond input signal by the shift register, processing informationassociated with the first input signal and the second input signal, andgenerating a digital signal based on at least information associatedwith the first input signal and the second input signal by an M-sequenceprocess. For example, the m-stage M-sequence generator can provide themaximum length pseudo-random number for a given m-stage and maximize therandomization. Moreover, the method includes processing informationassociated with the digital signal, and generating an analog signalrelated to a signal strength based on at least information associatedwith the digital signal. The digital signal represents at least an N-bitdatum, and N is a positive integer. The N-bit datum represents apseudorandom number. For example, the method can be performed by thesystem 100, 300, 400, and/or 1700.

The present invention has various advantages. Some embodiments of thepresent invention can reduce electromagnetic interference of aswitch-mode power converter. For example, the switch-mode converter isan off-line power converter. Certain embodiments of the presentinvention provide switching frequency variations to a switch-mode powerconverter. Some embodiments of the present invention avoid a strongsingle tone at a fixed frequency and the harmonics in a switch-modepower converter. Certain embodiments of the present invention can spreadthe electromagnetic interference power within a frequency range for aswitch-mode power converter. For example, the randomization of theswitching frequency can make the EMI power spectrum substantiallyuniform in a frequency band around a mean switching frequency and thehigh order harmonics. Some embodiments of the present invention providefrequency variations according to a frequency modulation index M_(f).For example, the frequency modulation index M_(f) is determined by theEMI requirement of the switch-mode power converter.

Certain embodiments of the present invention use a digital circuit forfrequency variation. The digital circuit is portable, and can be easilymigrated for different integrated circuit manufacturing processes. Someembodiments of the present invention provide frequency variations to aclock signal by a pseudorandom signal. For example, the pseudorandomsignal is a M-sequence signal. Certain embodiments of the presentinvention use a frequency variation controller including an m-stageM-sequence generator and an N-bit digital-to-analog converter. Forexample, the m-stage M-sequence generator includes an m-stage linearshift register. In another example, the digital-to-analog converteroperates either in the voltage mode or the current mode. In yet anotherexample, the output of the digital-to analog converter is used tocontrol frequency variations of an oscillator in a switch-mode powerconverter. In yet another example, the clock signal generated by theoscillator is fed into the linear shift register.

Some embodiments of the present invention use an oscillator controlledby voltage or current signals. For example, the control signals aregenerated by a frequency variation generator and/or a dead-timecontroller. In another example, the oscillator generates a clock signaland a ramping signal. The clock signal and the ramping signal do nothave a constant frequency. The frequency is randomized and shuffled overtime. In yet another example, the charge and discharge current in theoscillator is modulated by a pseudorandom signal. The modulated chargeand discharge current determine the oscillation frequency and hence theswitching frequency in the switch-mode power converter.

Although specific embodiments of the present invention have beendescribed, it will be understood by those of skill in the art that thereare other embodiments that are equivalent to the described embodiments.Accordingly, it is to be understood that the invention is not to belimited by the specific illustrated embodiments, but only by the scopeof the appended claims.

1. A system for providing frequency control to a power converter, thesystem comprising: a pseudorandom signal generator configured togenerate a digital signal, the digital signal associated with at leastan N-bit datum, N being a positive integer; a digital-to-analogconverter configured to receive the digital signal and generate a firstcontrol signal; an output signal generator configured to receive thefirst control signal and generate at least a first output signalassociated with a frequency; a pulse-width-modulation generatorconfigured to receive at least the first output signal; wherein theN-bit datum represents a pseudorandom number.
 2. The system of claim 1wherein the pseudorandom signal generator includes an m-stage M-sequencegenerator, m being a positive integer; the m-stage M-sequence generatoris configured to receive the first output signal.
 3. The system of claim1 wherein: the first output signal is associated with a first signalstrength; the frequency is inversely proportional to a first time periodand a second time period; the first signal strength during a first timeperiod is different from the first signal strength during the secondtime period.
 4. The system of claim 1 wherein the output signalgenerator is configured to change the frequency with respect to timewithin a predetermined frequency range.
 5. The system of claim 4 whereinthe frequency is associated with a mean frequency for a predeterminedtime period.
 6. The system of claim 1 wherein the first control signalincludes a pseudorandom signal.
 7. The system of claim 6 wherein theoutput signal generator is further configured to change the frequencywith respect to time based on at least information associated with thepseudorandom signal.
 8. The system of claim 7 wherein the frequencychanges randomly with respect to time.
 9. The system of claim 1 whereinthe first control signal is in at least one domain selected from a groupconsisting of a voltage domain and a current domain.
 10. The system ofclaim 1 wherein the pulse-width-modulation generator is configured tocontrol a switching frequency and a pulse width for a power converterbased on at least information associated with the first output signal.11. The system of claim 1, and further comprising a first controllerconfigured to receive a load signal and generate a second controlsignal, the load signal indicating an output load for a power converter.12. The system of claim 11 wherein: the frequency changes with respectto time; the frequency is associated with a mean frequency.
 13. Thesystem of claim 12 wherein the output signal generator is furtherconfigured to receive the second control signal and determine the meanfrequency based on at least information associated with the secondcontrol signal.
 14. The system of claim 1, and further comprising acompensation system configured to receive an input signal for a powerconverter and generate a third control signal.
 15. The system of claim14 wherein: the output signal generator is further configured to receivethe third control signal and generate a second output signal associatedwith a slope; wherein the generate a second output signal includesdetermine the slope based on at least information associated with thethird control signal.
 16. The system of claim 15 wherein thepulse-width-modulation generator uses the second output signal toperform a slope compensation for a feedback loop.
 17. The system ofclaim 16 wherein the slope compensation is associated with a slopecompensation ratio, the slope compensation ratio being constant withrespect to the input signal.
 18. The system of claim 14 wherein thecompensation system comprises: a sensing system configured to receivethe input signal and generate a fourth control signal; a compensationcontroller configured to receive the fourth control signal and outputthe third control signal.
 19. A system for providing a pseudorandomsignal, the system comprising: a shift register configured to receive afirst input signal and a second input signal and generate a digitalsignal, the shift register including m flip-flops, m being a positiveinteger; a processing device configured to receive a plurality ofsignals and generate the first input signal, the plurality of signalsrepresenting data stored in a plurality of flip-flops respectively, theplurality of flip-flops being selected from the m flip-flops; adigital-to-analog converter configured to receive the digital signal andgenerate an analog signal associated with a signal strength; wherein:the digital signal represents at least an N-bit datum, N being apositive integer; the N-bit datum corresponds to N flip-flops, the Nflip-flops being selected from the m flip-flops.
 20. The system of claim19 wherein the processing device is configured to perform anexclusive-OR operation.
 21. The system of claim 19 wherein thedigital-to-analog converter is further configured to receive a controlsignal and determine a first range for the signal strength.
 22. Thesystem of claim 21, and further comprising: an output signal generatorconfigured to receive the analog signal and generate at least an outputsignal associated with a frequency; a pulse-width-modulation generatorconfigured to receive at least the output signal; wherein the outputsignal and the second input signal are the same.
 23. The system of claim22 wherein the frequency changes within a second range, the second rangecorresponding to the first range.
 24. A method for providing frequencycontrol to a power converter, the method comprising: generating adigital signal, the digital signal associated with at least an N-bitdatum, N being a positive integer; receiving the digital signal;processing information associated with the digital signal; generating afirst control signal based on at least information associated with thedigital signal, the first control signal being an analog signal;receiving the first control signal; processing information associatedwith the first control signal; generating at least a first output signalrelated to a frequency based on at least information associated with thefirst control signal; wherein the N-bit datum represents a pseudorandomnumber.
 25. The method of claim 24 wherein the generating a digitalsignal includes generating the digital signal based on at leastinformation associated with the first output signal.
 26. The method ofclaim 24 wherein: the first output signal is associated with a firstsignal strength; the frequency is inversely proportional to a first timeperiod and a second time period; the first signal strength during afirst time period is different from the first signal strength during thesecond time period.
 27. The method of claim 24 wherein the frequencychanges with respect to time within a predetermined frequency range. 28.The method of claim 27 wherein the frequency is associated with a meanfrequency for a predetermined time period.
 29. The method of claim 24wherein the first control signal includes a pseudorandom signal.
 30. Themethod of claim 29 wherein the frequency changes with respect to timebased on at least information associated with the pseudorandom signal.31. The method of claim 30 wherein the frequency changes randomly withrespect to time.
 32. The method of claim 24, and further comprising:processing information associated with the first output signal;adjusting a switching frequency for a power converter based on at leastinformation associated with the first output signal.
 33. A method forproviding a pseudorandom signal, the method comprising: receiving aplurality of signals from a shift register; processing informationassociated with the plurality of signals; generating a first inputsignal based on at least information associated with the plurality ofsignals; receiving the first input signal and a second input signal bythe shift register; processing information associated with the firstinput signal and the second input signal; generating a digital signalbased on at least information associated with the first input signal andthe second input signal by an M-sequence process; processing informationassociated with the digital signal; generating an analog signal relatedto a signal strength based on at least information associated with thedigital signal; wherein: the digital signal represents at least an N-bitdatum, N being a positive integer; the N-bit datum represents apseudorandom number.
 34. The method of claim 33 wherein the generating afirst input signal includes performing an exclusive-OR operation. 35.The method of claim 33, and further comprising: receiving a controlsignal; processing information associated with the control signal;determining a first range for the signal strength based on at leastinformation associated with the control signal.
 36. The method of claim35, and further comprising: receiving the analog signal; processinginformation associated with the analog signal; generating at least anoutput signal related to a frequency based on at least informationassociated with the analog signal; wherein the output signal and thesecond input signal are the same.
 37. The method of claim 36 wherein thefrequency changes within a second range, the second range correspondingto the first range.